This invention is concerned with digital to analog converters. More particularly, it is concerned in one aspect with improving the architecture of segmented digital to analog converters and in another aspect with providing digital to analog converters having an analog output voltage which is a monotonic function of a digital input word.
A digital to analog converter (DAC) having a segmented structure typically operates by dividing a digital input word into subwords which control different parts of the DAC circuit. For example, a digital input word might be divided into a more significant (MS) subword and a less significant (LS) subword, the MS subword being used to generate a first intermediate current or voltage signal that is summed with a second intermediate current or voltage signal generated responsive to the LS subword. Such segmented structures are particularly useful for reducing the number of resistive elements required to provide a DAC with high resolution (e.g., 12 bits). However, summing the intermediate signals without buffering the outputs of the signal generating circuits may subject the outputs of the signal generating circuits to excessive load conditions. On the other hand, adding such buffering to the output of each signal generating circuit typically introduces noise and adds to the cost and complexity of the DAC.
Another potential problem which can be exacerbated by providing a buffer at the output of each signal generating circuit is non-monotonicity in the transfer characteristics of the DAC. In an ideal digital to analog converter (DAC), the analog output voltage should be a monotonic function of the digital input; that is, an increase in the digital input should lead to an increase in the analog output voltage, and a decrease in the digital input should lead to a decrease in the analog output voltage. Monotonicity is vital in many applications such as in control systems where non-monotonic DACs can create serious problems. In many practical cases, however, due to unavoidable component inaccuracies in the DACs, monotonicity is not always obtained.
Consider, for example, a typical 4-bit DAC which uses simple binary weighting to generate an analog output voltage by adding together binary multiples of 0.5, 0.25, 0.125, and 0.0625 volts. It is well known that, with this choice of weights, an increase in the digital input will always lead to an increase in the analog output.
For example, in such a DAC, a digital input string of 0111 would generate an analog output voltage of 0(0.5)+1(0.25)+1(0.125)+1(0.0625)=0.4375 volts. If the digital input is incremented to 1000, the analog output voltage increases to 1(0.5)+0(0.25)+0(0.125)+0(0.0625)=0.5 volts. Thus, as expected, an increment in the digital input results in an increase in the analog output.
However, if the binary weights are inaccurate, due for example to resistive element inaccuracies, this monotonic relationship between input and output may be lost. Suppose that the weights are actually 0.47, 0.27, 0.14, and 0.07 volts instead of their ideal values given above. In this case, the analog output voltage corresponding to a digital input of 0111 is 0(0.47)+1(0.27)+1(0.14)+1(0.07)=0.48 volts. When the digital input is incremented to 1000, the analog output voltage actually decreases to 1(0.47)+0(0.27)+0(0.14)+0(0.07)=0.47 volts. Thus, the analog output voltage in this case is not a monotonic function of the digital input.
The errors described above which lead to non-monotonic input/output relationships are particularly prevalent in DACs which sum together many binary weighted voltages, i.e., DACs having many bits. Yet it is precisely these devices that are required to provide accurate, monotonic digital to analog conversion.
In view of the foregoing, it would be desirable to provide a segmented DAC which is simple to implement and which provides immunity to loading problems associated with unbuffered analog summing of intermediate signals.
It would further be desirable to provide a segmented DAC which does not require a separate buffer circuit between the output of each signal generating circuit and the summing circuitry of the DAC.
It would also be desirable to provide a circuit for converting a digital input word into an analog output voltage in such a way that the analog output voltage is a monotonic function of the digital input word.